AMD announced a major milestone in its data center strategy. The company has taped out and brought up its next-generation EPYC processor, codenamed “Venice,” using TSMC’s advanced 2nm (N2) process technology.

This marks the first high-performance computing (HPC) product in the industry to reach this stage on the N2 node. It reflects the strong collaboration between AMD and TSMC to co-optimize chip design and manufacturing processes.

“Venice” remains on track to launch next year. It represents a key step forward in AMD’s CPU roadmap for data centers.

At the same time, AMD confirmed the successful bring-up and validation of its 5th Gen EPYC processor at TSMC’s new Arizona fabrication facility. This demonstrates AMD’s ongoing commitment to strengthening U.S.-based semiconductor manufacturing.

Dr. Lisa Su, AMD Chair and CEO, said the company’s partnership with TSMC continues to drive performance and innovation. She emphasized that AMD’s early access to the 2nm process and Arizona fab shows the depth of the collaboration.

TSMC Chairman and CEO Dr. C.C. Wei noted that AMD’s position as a lead HPC customer highlights shared efforts to improve performance, efficiency, and silicon yields.

Together, AMD and TSMC are shaping the future of computing through advanced technology and strategic manufacturing alignment. The EPYC processor roadmap continues to evolve with innovation at every step.

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